This application claims priority to Korean Patent Application No. 2001-71800, filed on Nov. 19, 2001.
1. Technical Field
The present invention relates to semiconductor memory devices and, in particular, to a semiconductor memory device comprising a shared sense amplifier structure, which prevents coupling noise between adjacent bit lines in different columns.
2. Description of Related Art
FIG. 1 is a block diagram of a semiconductor memory device. A semiconductor memory device 10 comprises a memory block 12 having a plurality of columns. Each column comprises a pair of bit lines and a plurality of memory cells such as DRAM, SRAM, or EEPROM cells.
For example, first through fourth columns each comprise a pair of bit lines DB0 and DBb0, UB0 and UBb0, DB1 and DBb1, and UB1 and UBb1, respectively. Odd-numbered and even-numbered columns are alternatively arranged in the memory block 12. Eight pairs of bit lines are shown in FIG. 1 for purposes of illustration, and it is to be understood that the memory can comprise additional pairs of bit lines arranged therein.
Each of the bit line pairs DB0/DBb0, DB1/DBb1, DB2/DBb2, and DB3/DBb3, of the odd-numbered columns (first, third, fifth and seventh columns) is connected to a corresponding bit line precharging and equalizing circuit 14, bit line isolating circuit 16, and sense amplifier 18.
For example, the bit line precharging and equalizing circuit 14 for bit line pair DB0/DBb1 comprises three NMOS transistors M1, M2, and M3. The bit line precharging and equalizing circuit 14 precharges and equalizes the bit lines to a predetermined voltage (e.g., xc2xd VCC voltage) in response to a control signal PEQi. Each bit line isolating circuit 16 is connected to a corresponding bit line pair to selectively connect the bit lines to a corresponding sense amplifier 18. Each bit line isolating circuit 16 comprises NMOS transistors M4 and M5 that are simultaneously activated/deactivated in response to a control signal PISOi.
Each sense amplifier 18 comprises a latch-type sense amplifier and is connected to a corresponding bit line pair and to voltage lines LA and LAb. The voltage line LAb is connected to ground voltage through an NMOS transistor M10, which is activated in response to a control signal LANG output from a control block 20. The voltage line LA is connected to power supply voltage for array Varray through a PMOS transistor M11, which is activated in response to a control signal LAPG output from the control block 20. The control block 20 generates the control signals LANG and LAPG in response to a complementary sense enable signal {overscore (BLSA_en)}.
Further, each bit line pair UB0/UBb0, UB1/UBb1, UB2/UBb2, and UB3/UBb3 (which correspond to even-numbered columns) are connected to a corresponding bit line precharging and equalizing circuit 22, a bit line isolating circuit 24, and a sense amplifier 26. The circuits 22, 24 and 26 have the same configurations as circuits 14, 16 and 18.
FIG. 2 is a circuit diagram of the control block 20 of FIG. 1. FIG. 3 depicts exemplary waveforms of the control signals of FIG. 2. The control block 20 comprises an inverter INV1, a delay element 21, and a NAND gate G1, and generates control signals LANG and LAPG in response to the sense enable signal {overscore (BLSA_en)}. When the sense enable signal {overscore (BLSA_en)} transitions from a high level to a low level, the control signal LANG is activated at a high level as illustrated in FIG. 3. In response to the activation of the control signal LANG, the NMOS transistor M10 (FIG. 1) is activated, thereby supplying ground voltage to the voltage line LAb. The control signal LANG is delayed by delay element 21. The delayed control signal and the control signal LANG are NAND gated by gate G1 to generate the control signal LAPG. When the control signal LAPG transitions from a high level to a low level, the PMOS transistor M11 (shown in FIG. 1) is activated, thereby supplying power supply voltage for array Varray to the voltage line LA.
In the semiconductor memory device 10, coupling noise is generated between adjacent bit lines in adjacent columns, as indicated by the dotted circles that connect adjacent bit lines in FIG. 1. The bit line pair of each column, which comprises a true bit line and a complement bit line, receives data from a memory cell in response to the activation of a row or a word line connected to the memory cell.
FIG. 4A is an exemplary diagram illustrating coupling noise that is generated in the semiconductor memory device 10. For example, when the memory cell storing data xe2x80x981xe2x80x99 is sensed, a precharge voltage of the true bit line UB0 of the second column connected to the memory cell is increased by the voltage corresponding to the data xe2x80x981xe2x80x99. The complement bit line UBb0 of the true bit line UBO maintains the precharged voltage. When the control signal LANG is activated, a voltage of a bit line having a relatively lower voltage, that is, the voltage of the complement bit line UBb0, is lowered to ground voltage. When the control signal LAPG is activated, a voltage of a bit line having a relatively higher voltage, that is, the voltage of the true bit line UB0 is increased to the power supply voltage for array Varray.
When a memory cell connected to a true bit line (e.g., the true bit line DB1 of the third column) of an adjacent column to the second column stores data xe2x80x981xe2x80x99, the precharged voltage of the true bit line DB1 is increased by the voltage corresponding to the data xe2x80x981xe2x80x99. The corresponding complement bit line DBb1 maintains the precharged voltage. When the control signal LANG is activated, a voltage of a bit line having a relatively lower voltage, that is, the voltage of the complement bit line DBb1, is lowered to the ground voltage. When the control signal LAPG is activated, a voltage of a bit line having a relatively higher voltage, that is, the voltage of the true bit line DB1 is increased to the power supply voltage for array Varray.
A coupling capacitor is formed between the adjacent bit lines UBb0 and DB1 of the adjacent pairs of bit lines UB0 and UBb0, and DB1 and DBb1 of the second and third columns. When the voltage of the complement bit line UBb0 of the second column is lowered to the ground voltage in response to the activation of the control signal LANG, the voltage of the true bit line DB1 of the third column is instantly lowered by the coupling capacitor, as illustrated in FIG. 4A. This phenomenon is called xe2x80x9ccoupling noisexe2x80x9d, which generates erroneous data.
The coupling noise also occurs when a memory cell storing data xe2x80x980xe2x80x99 is sensed. Referring to FIG. 4B, when the memory cell storing data xe2x80x980xe2x80x99 is sensed, the true bit line UB3 of the eighth column connected to the memory cell stores the data xe2x80x980xe2x80x99. The precharged voltage of the true bit line UB3 is lowered by the voltage corresponding to the data xe2x80x980xe2x80x99, while the corresponding complement bit line UBb3 maintains the precharged voltage. In response to the activation of the control signal LANG, a voltage of a bit line having a relatively lower voltage, that is, the voltage of the true bit line UB3, is lowered to the ground voltage. In response to the activation of the control signal LAPG, a voltage of a bit line having a relatively higher voltage, that is, the voltage of the complement bit line UBb3, is increased to the power supply voltage for array Varray.
When the memory cell connected to a column (e.g., the seventh column) that is adjacent to the eighth column stores data xe2x80x980xe2x80x99, the precharged voltage of the true bit line DB3 of the seventh column is lowered by the voltage corresponding to the data xe2x80x980xe2x80x99. The corresponding complement bit line DBb3 maintains the precharged voltage. In response to the activation of the control signal LANG, a voltage of a bit line having a relatively lower voltage, that is, the voltage of the true bit line DB3, is lowered to the ground voltage. In response to the activation of the control signal LAPG, a voltage of a bit line having a relatively higher voltage, that is, the voltage of the complement bit line DB3, is increased to the power supply voltage for array Varray.
When the voltage of the true bit line UB3 is lowered to the ground voltage in response to the activation of the control signal LANG, the voltage of the complement bit line DBb3 is instantly lowered through the coupling capacitor, as illustrated in FIG. 4B, thereby generating erroneous data.
Thus, a need exists for preventing the generation of the coupling noise between adjacent bit lines in different columns.
It is an object of the invention to provide a semiconductor memory device that prevents coupling noise from being generated between adjacent bit lines in different columns.
According to one aspect of the present invention, a semiconductor memory device comprises first and second columns, wherein each column comprises a pair of bit lines, and wherein the first and second columns are adjacent, a first sense amplifier, connected to the bit lines of the first column, for sensing and amplifying a voltage difference between the bit lines of the first column, a second sense amplifier, connected to the bit lines of the second column, for sensing and amplifying a voltage difference between the bit lines of the second column, and a control circuit for controlling the first and second sense amplifiers, wherein when voltage levels of adjacent bit lines of the first and second columns transition in an opposite direction during a read operation, the control circuit controls the first and second sense amplifiers to concurrently amplify the voltages of the adjacent bit lines.
In a preferred embodiment of the present invention, when the voltage levels of the adjacent bit lines of the first and second columns transition in the same direction during the read operation, the control circuit controls the first and second sense amplifiers to amplify the voltages of the adjacent bit lines at different times within a predetermined interval.
According to another aspect of the present invention, a semiconductor memory device comprises an array of memory blocks each comprising a plurality of columns, each column comprising a pair of bit lines, a plurality of sense amplifier blocks, wherein first and second sense amplifier blocks are disposed on opposite sides of a corresponding memory block, wherein each sense amplifier block comprises a plurality of sense amplifiers connected to columns of the corresponding memory block, wherein adjacent columns are connected to sense amplifiers on opposite sides of the memory block, and a control circuit for controlling the first and second sense amplifier blocks, wherein when voltage levels of adjacent bit lines of adjacent columns of a memory block transition in an opposite direction during a read operation, the control circuit controls the first and second sense amplifier blocks to concurrently amplify the voltages of the adjacent bit lines.
In a preferred embodiment of the present invention, when the voltage levels of adjacent bit lines of adjacent columns transition in the same direction during the read operation, the control circuit controls the first and second sense amplifier blocks to amplify the voltages of the adjacent bit lines at different times within a predetermined time interval.
According to further aspect of the present invention, a method for preventing coupling noise from being generated in a semiconductor memory device, comprises sensing voltage differences between the bit lines in the first and second columns, respectively, and concurrently amplifying voltages of adjacent bit lines of the first and second columns, when the voltage levels of the adjacent bit lines of the first and second columns transition in an opposite direction during a read operation.
In a preferred embodiment of the present invention, the method further comprises amplifying the voltages of the adjacent bit lines of the first and second columns at different times within a predetermined time interval, when the voltage levels of the adjacent bit lines of the first and second columns transition in the same direction during the read operation.
These and other aspects, features, and advantages of the present invention will become apparent from the following detailed description of preferred embodiments, which is to be read in conjunction with the accompanying figures.